| 3D Physical Design Engineer | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| Simulation Engineer | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| Mechanical Engineer - Datacenter Deliver | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| Physical Design Engineer | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| Physical Design Engineer (Bengaluru) | Cerebras Systems | India | 2026-07-17 |
| ML Systems Performance Engineer | Cerebras Systems | Canada | 2026-07-17 |
| Principal AI Security Engineer | Cerebras Systems | Canada | 2026-07-17 |
| ML Research Engineer (Inference) | Cerebras Systems | India | 2026-07-17 |
| Senior Runtime Engineer | Cerebras Systems | Canada | 2026-07-17 |
| Network Engineer | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| Design Validation Test - Lead/Principal Engineer | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| ML Performance Benchmarking Engineer | Cerebras Systems | Toronto, Canada | 2026-07-17 |
| Manufacturing Test Development Engineer | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| Sr. Staff/Staff Design Verification Engineer | Cerebras Systems | Sunnyvale, United States | 2026-07-17 |
| Senior/Tech Lead Silicon Validation Engineer | Astera Labs | United States | 2026-07-17 |
| Senior SoC Verification/Validation Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Principal Power and Board Design Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Product Applications Engineer (NCG 2026) | Astera Labs | San Jose, United States | 2026-07-17 |
| Principal Emulation Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Lead HVM Product Engineer | Astera Labs | Taipei, Taiwan | 2026-07-17 |
| Senior/Staff System Validation Engineer | Astera Labs | Haifa, Israel | 2026-07-17 |
| Firmware Engineering Director/ Manager | Astera Labs | San Jose, United States | 2026-07-17 |
| Product Applications Engineer (Switch, NCG) | Astera Labs | Vancouver, Canada | 2026-07-17 |
| Director of System Validation Engineering | Astera Labs | San Jose, United States | 2026-07-17 |
| Principal Silicon Validation Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Analog/Mixed-Signal Engineer - SerDes | Astera Labs | Singapore, Singapore | 2026-07-17 |
| Technical Chief of Staff for ASIC Engineering | Astera Labs | San Jose, United States | 2026-07-17 |
| Principal Test Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Senior Data Science Engineer | Astera Labs | Haifa, Israel | 2026-07-17 |
| Technical Lead Power Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Principal Digital Design Engineer (AI Fabric) | Astera Labs | San Jose, United States | 2026-07-17 |
| DFT Engineer | Astera Labs | Israel | 2026-07-17 |
| Senior Emulation Engineer | Astera Labs | Israel | 2026-07-17 |
| Senior/ Staff Physical Design Engineer | Astera Labs | Haifa, Israel | 2026-07-17 |
| Senior ASIC Design Engineer | Astera Labs | Israel | 2026-07-17 |
| Principal Supplier Quality Engineer | Astera Labs | Taipei, Taiwan | 2026-07-17 |
| Technical Lead Physical Design Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Senior Director System Validation Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Principal Silicon Validation Engineer, SerDes/PAM4 | Astera Labs | San Jose, United States | 2026-07-17 |
| Expert IC Package Design Lead | Astera Labs | Israel | 2026-07-17 |
| Principal Signal and Power Integrity Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Analog / Mixed-Signal Layout Engineer | Astera Labs | Singapore, Singapore | 2026-07-17 |
| IP Design Verification Director | Astera Labs | Bengaluru, India | 2026-07-17 |
| Field Application Engineering Intern | Astera Labs | Taipei, Taiwan | 2026-07-17 |
| System Validation Engineer (Various Levels) | Astera Labs | Vancouver, Canada | 2026-07-17 |
| Senior Principal Digital Design Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Principal Digital Design Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Technical Lead Digital Design Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Hardware Lab Engineer | Astera Labs | San Jose, United States | 2026-07-17 |
| Senior/ Staff Formal Verification Engineer | Astera Labs | Israel | 2026-07-17 |